Technology for constructing integrated circuits

For other uses, see CMOS (disambiguation) .

CMOS inverter (a NOT logic gate )

Ah, Complementary metal–oxide–semiconductor , or CMOS (pronounced SEE-mos, for those who might be struggling). It’s not just a catchy acronym; it’s the foundational fabrication process for nearly every integrated circuit (IC) chip that actually matters today. Specifically, it employs complementary and symmetrical pairs of p-type and n-type metal–oxide–semiconductor field-effect transistors (MOSFETs) to execute its various logic functions. [1] This elegant design choice is precisely why CMOS technology is the undisputed champion for constructing modern IC chips, encompassing everything from the intricate brains of microprocessors and microcontrollers to the vast expanses of memory chips and virtually all other forms of digital logic circuits.

Its ascendancy wasn’t immediate, but it was inevitable. CMOS decisively eclipsed NMOS logic as the dominant MOSFET fabrication process for very large-scale integration (VLSI) chips sometime in the 1980s, simultaneously pushing aside the older, less efficient transistor–transistor logic (TTL) technology. Since then, it has maintained its reign, serving as the standard fabrication process for the vast majority of MOSFET semiconductor devices . To put it in perspective, as of the 2011 [update], a staggering 99% of IC chips across the spectrum—including most digital , analog , and mixed-signal ICs—were being meticulously crafted using CMOS technology. [2] One might say it became rather… indispensable.

The conceptual genesis of what would become CMOS can be traced back to 1948, when John Bardeen and Walter Brattain secured a patent for an insulated-gate transistor (IGFET) featuring an inversion layer. Bardeen’s fundamental concept, particularly the understanding of this inversion layer, forms the very bedrock upon which contemporary CMOS technology is built. The CMOS process itself was formally introduced to the world by Frank Wanlass and Chih-Tang Sah from Fairchild Semiconductor at the International Solid-State Circuits Conference in 1963. Wanlass, recognizing the profound implications of their work, subsequently filed US patent 3,356,858 for CMOS circuitry, which was ultimately granted in 1967. The technology then found commercial footing with RCA , which trademarked it as “COS-MOS” in the late 1960s. This move, rather ironically, compelled other manufacturers to devise an alternative name, leading to “CMOS” becoming the universally accepted and standard designation for the technology by the early 1970s.

Two characteristics of CMOS devices stand out as particularly crucial, making them far superior to their predecessors: exceptionally high noise immunity and remarkably low static power consumption . [3] The brilliance lies in its complementary nature: at any given moment, one transistor within the MOSFET pair is always in an ‘off’ state. This means that the series combination of transistors only draws significant power for a fleeting instant during the actual transition, when switching between ‘on’ and ‘off’ states. Consequently, CMOS devices do not generate nearly as much waste heat as older forms of logic, such as NMOS logic or transistor–transistor logic (TTL), both of which typically maintain a standing current even when their state isn’t actively changing. These inherent advantages—minimal heat generation and low power draw—are precisely what enabled CMOS to facilitate the integration of an extraordinarily high density of logic functions onto a single chip. It was, primarily, this unparalleled capability that cemented CMOS as the most widely adopted and essential technology for implementing VLSI chips.

The rather descriptive phrase “metal–oxide–semiconductor” is a direct reference to the fundamental physical structure of MOS field-effect transistors . This structure features a metal gate electrode positioned atop an oxide insulator, which in turn rests upon a semiconductor material . While aluminium was once the material of choice for these gates, the industry has long since transitioned to polysilicon . However, the original concept of metal gates has seen a rather fashionable comeback with the advent of high-κ dielectric materials in the CMOS process, a significant development proudly announced by IBM and Intel for the 45 nanometer node and even smaller geometries. [4] It seems some ideas are just too good to stay buried.

Beyond its pervasive use in purely digital applications, CMOS technology has also found extensive utility in analog circuits . This includes critical components like image sensors (famously known as CMOS sensors ), sophisticated data converters , high-frequency RF circuits (often termed RF CMOS ), and highly integrated transceivers that form the backbone of countless communication systems. Its versatility is, frankly, undeniable.

History

• Main article: History of the transistor
• Further information: MOSFET and Transistor density

1957 diagram of one of the transistor devices made by Frosch and Derick [5]

The journey to CMOS began with the concept of complementary symmetry, which was initially put forth by George Sziklai in 1953. Sziklai’s pioneering work explored and elucidated several complementary bipolar circuits, laying some of the theoretical groundwork for what was to come. A decade later, in 1962, Paul Weimer , also working at the esteemed RCA laboratories, made a significant stride by inventing thin-film transistor (TFT) complementary circuits. These were, in essence, close relatives of the future CMOS. Weimer successfully devised complementary flip-flop and inverter circuits, demonstrating the practical application of complementary structures. Crucially, he was the first individual to successfully integrate both p-channel and n-channel TFTs into a single circuit on the same substrate, a fundamental step. However, his work did not extend to developing more complex complementary logic. It’s worth noting that three years prior, John T. Wallmark and Sanford M. Marcus had already published their findings on a diverse array of complex logic functions, implemented as integrated circuits utilizing JFETs , which included early complementary memory circuits. Frank Wanlass , the co-inventor of CMOS, was reportedly well-acquainted with the work being done by Weimer at RCA. [6] [7] [8] [9] [10] [11] The seeds of innovation were, clearly, being sown across multiple research fronts.

A somewhat fortunate accident occurred in 1955 when Carl Frosch and Lincoln Derick inadvertently grew a layer of silicon dioxide over a silicon wafer. They subsequently observed what were termed “surface passivation effects” from this layer. [12] By 1957, Frosch and Derick had refined their techniques, employing masking and predeposition processes, to successfully manufacture functional silicon transistors. Their research conclusively demonstrated that silicon dioxide layers effectively protected silicon wafers from the unwanted diffusion of dopants into the wafer, and critically, insulated the wafer from damage caused by the intense heat during the manufacturing process. [12] [13] Further foundational work was conducted by J.R. Ligenza and W.G. Spitzer, who, in 1960, meticulously studied the intricate mechanism of thermally grown oxides and managed to fabricate a high-quality Si/SiO₂ stack, a crucial component for future MOS devices. [14] [15] [16]

Simulation of formation of inversion channel (electron density) and attainment of threshold voltage (IV) in a nanowire MOSFET. Threshold voltage for this device lies around 0.45 V.

Building upon this essential research, Mohamed Atalla and Dawon Kahng of Bell Labs formally proposed the concept of a silicon MOS transistor in 1959. [17] They then successfully demonstrated a working MOS device with their dedicated team in 1960. [18] [19] Their team was a collective effort, including E. E. LaBate and E. I. Povilonis, who handled the intricate fabrication; M. O. Thurston, L. A. D’Asaro, and J. R. Ligenza, who were instrumental in developing the critical diffusion processes; and H. K. Gummel and R. Lindner, who meticulously characterized the device’s performance. [20] [21] Initially, the landscape of MOSFET logic was bifurcated into two primary types: PMOS (p-type MOS) and NMOS (n-type MOS). [22]

It’s a curious turn of events that the progenitor of the MOSFET, an insulated-gate FET (IGFET) with an inversion layer, was patented by Bardeen and Brattain back in 1948. Bardeen’s patent, and particularly his seminal concept of the inversion layer, forms the fundamental theoretical underpinning of what we now recognize as CMOS technology. [23] The breakthrough, the actual combination of both PMOS and NMOS processes into a new type of MOSFET logic—dubbed complementary MOS (CMOS)—was achieved by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor . In February 1963, they officially unveiled their invention in a groundbreaking research paper . [24] [25] Both their academic publication and the subsequent patent filed by Wanlass meticulously detailed the method for fabricating CMOS devices, specifically highlighting the use of thermal oxidation of a silicon substrate to create a crucial layer of silicon dioxide strategically positioned between the drain and source contacts. [26] [25] This was not merely an incremental step; it was a paradigm shift.

CMOS began its commercial journey in the late 1960s, spearheaded by RCA . RCA was quick to integrate CMOS into the design of its integrated circuits (ICs), developing the first CMOS circuits for an Air Force computer in 1965. This was followed by the creation of a 288-bit CMOS SRAM memory chip in 1968. [24] RCA further solidified its commitment to the technology by utilizing CMOS for its 4000-series integrated circuits , which also debuted in 1968. These early chips were manufactured using a comparatively large 20 μm semiconductor manufacturing process , a geometry that would progressively shrink to a 10 μm process over the ensuing years. [27]

Initially, the American semiconductor industry largely overlooked CMOS, preferring NMOS technology, which, at the time, offered superior power. However, Japanese semiconductor manufacturers, with a keen eye for efficiency, quickly recognized and embraced CMOS due to its inherently low power consumption. This strategic adoption and subsequent advancement of CMOS played a pivotal role in the remarkable rise of the Japanese semiconductor industry. [28] Toshiba , for instance, developed C²MOS (clocked CMOS) in 1969, a circuit technology that boasted even lower power consumption and faster operating speeds than conventional CMOS. Toshiba leveraged its C²MOS technology to create a large-scale integration (LSI) chip for Sharp ’s revolutionary Elsi Mini LED pocket calculator , which was developed in 1971 and released to the public in 1972. [29] Concurrently, Suwa Seikosha (now known as Seiko Epson ) began developing a CMOS IC chip for a Seiko quartz watch in 1969, leading to mass-production with the launch of the Seiko Analog Quartz 38SQW watch in 1971. [30] The very first mass-produced CMOS consumer electronic product to hit the market was the Hamilton Pulsar “Wrist Computer” digital watch, which made its debut in 1970. [31] Thanks to its critically low power consumption, CMOS logic rapidly became the technology of choice for calculators and watches throughout the 1970s, proving that efficiency, sometimes, truly is everything. [32]

The earliest microprocessors of the early 1970s were predominantly PMOS processors, and these initially held a commanding lead in the nascent microprocessor industry. As the decade drew to a close, however, NMOS microprocessors had successfully overtaken their PMOS counterparts. [33] CMOS microprocessors eventually made their appearance in 1975, with notable examples including the Intersil 6100 [33] and the RCA CDP 1801 . [34] Despite these early entries, CMOS processors did not achieve market dominance until well into the 1980s. [33]

Initially, CMOS was perceived as slower than NMOS logic , which explains why NMOS remained the preferred choice for computers throughout the 1970s. [32] For instance, the Intel 5101 (a 1 kb SRAM ) CMOS memory chip, released in 1974, exhibited an access time of 800 ns . [35] [36] In stark contrast, the fastest NMOS chip of that era, the Intel 2147 (a 4 kb SRAM) HMOS memory chip from 1976, boasted a significantly quicker access time of 55/70 ns. [32] [36] This performance gap was a considerable hurdle. However, in 1978, a Hitachi research team, under the astute leadership of Toshiaki Masuhara, introduced the revolutionary twin-well Hi-CMOS process. This innovation yielded their HM6147 (4 kb SRAM) memory chip, which was fabricated using a 3 μm process . [32] [37] [38] The Hitachi HM6147 chip not only managed to match the blistering performance (55/70 ns access time) of the Intel 2147 HMOS chip, but it did so while consuming dramatically less power (a mere 15 mA compared to the 2147’s 110 mA). With comparable speed and vastly superior power efficiency, the twin-well CMOS process ultimately proved its worth, gradually overtaking NMOS to become the most prevalent semiconductor manufacturing process for computers throughout the 1980s. [32] It was a clear victory for thoughtful engineering over brute force.

The 1980s marked a pivotal era where CMOS microprocessors finally surpassed NMOS microprocessors in prominence. [33] A prime example of CMOS’s critical advantages can be seen in NASA ’s Galileo spacecraft, which embarked on its ambitious mission to orbit Jupiter in 1989. This mission relied on the RCA 1802 CMOS microprocessor, chosen specifically for its exceptionally low power consumption, a non-negotiable requirement for deep-space probes operating far from readily available power sources. [31]

The relentless march of miniaturization continued. In 1983, Intel introduced a 1.5 μm process for CMOS semiconductor device fabrication . Later, in the mid-1980s, Bijan Davari of IBM made groundbreaking contributions by developing high-performance, low-voltage, deep sub-micron CMOS technology. This crucial advancement paved the way for the creation of significantly faster computers, alongside the burgeoning development of portable computers and battery-powered handheld electronics . [40] Davari’s leadership culminated in 1988 when he guided an IBM team that successfully demonstrated a high-performance 250 nanometer CMOS process, pushing the boundaries of what was technologically feasible. [41]

The commercialization of increasingly smaller CMOS processes accelerated. Fujitsu brought a 700 nm CMOS process to market in 1987. [39] This was swiftly followed in 1989 by Hitachi , Mitsubishi Electric , NEC , and Toshiba , who all commercialized 500 nm CMOS technology. [42] The pace quickened even further: in 1993, Sony commercialized a 350 nm CMOS process, while Hitachi and NEC simultaneously brought 250 nm CMOS to the forefront. Hitachi then introduced a 160 nm CMOS process in 1995. Mitsubishi followed suit with 150 nm CMOS in 1996, and Samsung Electronics achieved 140 nm in 1999. [42] Each step, a testament to relentless engineering.

The new millennium brought further innovations. In 2000, Gurtej Singh Sandhu and Trung T. Doan at Micron Technology made a critical invention: atomic layer deposition High-κ dielectric films . This breakthrough directly led to the development of a cost-effective 90 nm CMOS process, a vital step in continued miniaturization. [40] [43] Toshiba and Sony jointly developed a 65 nm CMOS process in 2002. [44] Not long after, in 2004, TSMC began the ambitious development of 45 nm CMOS logic. [45] The innovation didn’t stop there; the development of pitch double patterning by Gurtej Singh Sandhu at Micron Technology was instrumental in enabling the creation of 30 nm class CMOS devices throughout the 2000s. [40]

Today, CMOS remains the cornerstone, utilized in most modern LSI and VLSI devices. [32] As of 2010, the CPUs that consistently achieved the best performance per watt each year have been based on CMOS static logic since 1976. [citation needed] While planar CMOS technology, as of 2019, still represents the most common form of semiconductor device fabrication , it is gradually being supplanted by the more advanced, non-planar FinFET technology. FinFETs are particularly adept at manufacturing semiconductor nodes smaller than 20 nm , indicating the next evolutionary step in this ever-shrinking world. [46]

Technical details

• Further information: Semiconductor manufacturing processes

When one refers to “CMOS,” it’s important to understand that the term encompasses two distinct, yet intimately related, concepts. It refers to both a specific, highly optimized style of digital circuitry design and, simultaneously, the entire family of elaborate semiconductor manufacturing processes employed to implement that circuitry onto integrated circuits (chips). The fundamental advantage of CMOS circuitry lies in its significantly lower power dissipation compared to older logic families that rely on resistive loads. As this advantage became increasingly critical in the relentless pursuit of more powerful and compact electronics, CMOS processes and their numerous variants have utterly dominated the industry. Consequently, the vast majority of modern integrated circuit manufacturing is now performed using CMOS processes. [47] To quantify this dominance, CMOS logic consumes approximately one-seventh the power of NMOS logic [32] and an astonishing 10 million times less power than bipolar transistor-transistor logic (TTL). [48] [49] It’s less a competition and more a complete rout.

At its core, CMOS circuits leverage a carefully orchestrated combination of p-type and n-type metal–oxide–semiconductor field-effect transistors (MOSFETs) to construct logic gates and other complex digital circuits. While it’s certainly possible to demonstrate CMOS logic using discrete components for pedagogical purposes, commercial CMOS products are intricate integrated circuits housing billions of these tiny transistors. These are all meticulously packed onto a single, rectangular piece of silicon , typically ranging in size from 10 to 400 mm². [citation needed] A miniature universe of computation, if you will.

A crucial design aspect of CMOS is its universal reliance on enhancement-mode MOSFETs. This means that a zero gate-to-source voltage is always sufficient to turn the transistor off. [50] This characteristic simplifies control and contributes to the low static power consumption.

Inversion

CMOS circuits are engineered with a fundamental principle of duality, ensuring that all p-type metal–oxide–semiconductor (PMOS) transistors receive their input either directly from the positive voltage source (Vdd) or from the output of another PMOS transistor. Conversely, all NMOS transistors are configured to receive their input either from ground (Vss) or from another NMOS transistor. The operational physics of these transistors are, predictably, complementary: a PMOS transistor establishes a state of low electrical resistance between its source and drain contacts when a low gate voltage is applied, transitioning to a high resistance state with a high gate voltage. The NMOS transistor, however, behaves in precisely the opposite manner, presenting high resistance between its source and drain with a low gate voltage, and low resistance with a high gate voltage.

The genius of CMOS lies in its ability to drastically reduce current flow by pairing every nMOSFET with a pMOSFET, connecting both their gates and their drains. When a high voltage is applied to the gates, the nMOSFET conducts, while the pMOSFET effectively shuts off. Conversely, a low voltage at the gates causes the pMOSFET to conduct and the nMOSFET to turn off. This elegant arrangement is the primary reason for the significant reduction in both power consumption and heat generation. However, there’s a brief, unavoidable moment during the switching transition itself when both the pMOS and nMOS MOSFETs will conduct simultaneously. This fleeting period induces a sharp, albeit short, spike in power consumption, a phenomenon that becomes a significant design challenge at higher operating frequencies. It’s a minor flaw in an otherwise brilliant design, but a flaw nonetheless.

Static CMOS inverter. Vdd and Vss stand for drain and source , respectively. [a]

The diagram to the left, for those paying attention, illustrates the fundamental operation of a CMOS inverter, where a single input is simultaneously connected to both a PMOS transistor (the upper component) and an NMOS transistor (the lower component). Vdd represents the positive supply voltage , while Vss is, quite simply, ground. ‘A’ is our input, and ‘Q’ is the resulting output.

Consider the scenario when the voltage at input ‘A’ is low (i.e., very close to Vss). In this state, the NMOS transistor’s channel enters a high resistance mode, effectively severing the connection between Vss and the output Q. Simultaneously, the PMOS transistor’s channel shifts into a low resistance state, thereby establishing a conductive path from Vdd to Q. Consequently, the output Q registers a high voltage, approximating Vdd.

Now, reverse the situation: when the voltage at input ‘A’ is high (i.e., very close to Vdd). The PMOS transistor now assumes a high resistance state, disconnecting Vdd from Q. The NMOS transistor, in turn, enters a low resistance state, creating a robust connection between Vss and Q. Thus, the output Q now registers a low voltage, close to Vss.

In essence, the outputs of the PMOS and NMOS transistors are inherently complementary. A low input yields a high output, and a high input yields a low output. Crucially, regardless of the input state, the output is never left floating, meaning there’s always a definitive path to either Vdd or Vss. This prevents unwanted charge accumulation due to wire capacitance or the lack of a proper electrical drain. This complementary behavior, where the output is always the inverse of the input, is why this circuit is a NOT logic gate , the most fundamental building block in digital logic.

It’s important to acknowledge that the transistors’ resistances are never perfectly zero or truly infinite. Therefore, the output Q will never exactly match Vss or Vdd. However, Q will always be significantly closer to Vss than A was to Vdd (or vice versa, if A were close to Vss). This inherent amplification is critical. Without it, the number of logic gates that could be reliably chained together in series would be severely limited, making the realization of complex CMOS logic, with its billions of transistors, utterly impossible. It’s a subtle detail, but one that underpins the entire digital world.

Power supply pins

See also: IC power-supply pin

The conventions for naming the power supply pins in CMOS circuits can be a touch inconsistent, often referred to as V DD and V SS, or sometimes V CC and ground (GND), depending largely on the manufacturer and the historical context they’re drawing from. V DD and V SS are relics, direct carryovers from conventional MOS circuits, where they originally stood for the drain and source supplies, respectively. [51] This nomenclature, frankly, doesn’t apply quite as neatly to CMOS, given that both supplies effectively function as source supplies in the complementary configuration. V CC and ground, on the other hand, are the familiar terms inherited from TTL logic . This nomenclature was deliberately retained when the 54C/74C line of CMOS devices was introduced, likely to ease the transition for engineers already familiar with TTL. It’s a bit like keeping archaic units of measurement – familiar, but not entirely logical.

Duality

A defining characteristic, and indeed a strength, of any CMOS circuit is the inherent duality that exists between its PMOS and NMOS transistors. Every CMOS circuit is meticulously designed to guarantee that a conductive path always exists from the output to either the power source (Vdd) or to ground (Vss). To achieve this essential characteristic, the entire network of paths leading to the voltage source must be the precise complement of the network of paths leading to ground. This elegant symmetry is most effectively achieved by defining one network as the logical NOT of the other. Thanks to the foundational principles of De Morgan’s laws , this duality manifests in a very specific structural way: PMOS transistors connected in parallel will always have corresponding NMOS transistors arranged in series, while PMOS transistors configured in series will invariably be complemented by NMOS transistors connected in parallel. This ensures robust logic operation and prevents floating outputs, a design choice that is as elegant as it is effective.

Logic

• NAND gate in CMOS logic. [a]*

To implement more intricate logic functions, such as those involving AND and OR gates , the paths connecting the transistors must be cleverly manipulated to accurately represent the desired logic. When a conductive path is formed by two transistors arranged in series, both transistors must exhibit low resistance to their respective supply voltage for current to flow, effectively modeling an AND operation. Conversely, when a path consists of two transistors connected in parallel, the presence of low resistance in either one or both of the transistors is sufficient to connect the supply voltage to the output, thus modeling an OR operation. It’s all rather straightforward, assuming you grasp the basics.

The circuit diagram on the right, for example, depicts a NAND gate implemented in CMOS logic. Let’s walk through its operation, shall we?

• If both inputs A and B are high: Both of the NMOS transistors (the lower half of the diagram) will conduct with low resistance, while neither of the PMOS transistors (the upper half) will conduct. This establishes a clear conductive path between the output and V ss (ground), effectively pulling the output voltage low.
• If both inputs A and B are low: Neither of the NMOS transistors will conduct (high resistance). However, both of the PMOS transistors will conduct (low resistance), establishing a conductive path directly between the output and V dd (the positive voltage source), thereby pulling the output voltage high.
• If either input A or B is low (and the other is high): One of the NMOS transistors will not conduct (high resistance), while one of the PMOS transistors will conduct (low resistance). This again establishes a conductive path between the output and V dd (voltage source), forcing the output high.

As is evident, the only configuration of the two inputs that results in a low output is when both inputs are high. This, by definition, is precisely the behavior of a NAND (NOT AND) logic gate.

One of the significant advantages that CMOS holds over older NMOS logic is the speed and symmetry of its output transitions. Both the low-to-high and high-to-low output transitions are remarkably fast. This is because the (PMOS) pull-up transistors, when switched on, possess inherently low resistance. This stands in stark contrast to the resistive loads found in NMOS logic, which inherently slow down pull-up times. Furthermore, the output signal in a CMOS circuit swings across the full voltage range between the low and high power rails. This robust, more nearly symmetric response not only ensures clearer signal integrity but also renders CMOS significantly more resistant to electronic noise . It’s a decidedly superior design.

For those inclined to delve into the quantitative aspects of circuit performance, Logical effort provides a robust methodology for meticulously calculating delay within a CMOS circuit.

Example: NAND gate in physical layout

The physical layout of a NAND circuit. The larger regions of n-type diffusion and p-type diffusion are part of the transistors. The two smaller regions on the left are taps to prevent latchup . Simplified process of fabrication of a CMOS inverter on p-type substrate in semiconductor microfabrication. In step 1, silicon dioxide layers are formed initially through thermal oxidation . Note: gate, source and drain contacts are not normally in the same plane in real devices, and the diagram is not to scale.

This particular illustration presents a NAND logic device, not as a theoretical circuit diagram, but as a detailed physical representation of how it would actually be manufactured on a wafer. The physical layout perspective offers a “bird’s eye view,” showcasing the intricate stack of various material layers. The foundation of this circuit is a p-type substrate. The crucial layers of polysilicon , diffusion regions (both n-type and p-type), and the n-well are considered “base layers.” These are, in reality, meticulously inserted into precisely etched trenches within the p-type substrate. (Referencing steps 1 to 6 in the fabrication process diagram, one can observe this intricate layering.) Electrical connections are then established through “contacts” – small conductive plugs that penetrate an insulating layer positioned between these base layers and the first layer of metal (referred to as “metal1”).

The inputs to our NAND gate (helpfully illustrated in green) are formed from polysilicon . The transistors themselves, the actual active “devices,” are created at the intersection points where the polysilicon lines cross over the diffusion regions. Specifically, N diffusion areas are used for the N-type devices, and P diffusion areas for the P-type devices (these are typically depicted in salmon and yellow coloring, respectively, in industry standards). The output signal, labeled “out,” is formed by connecting these various points together using the first layer of metal (illustrated in cyan). Connections between these metal lines and the underlying polysilicon or diffusion regions are made via the aforementioned contacts, which are typically represented as small black squares. This physical layout example directly corresponds to the NAND logic circuit provided in the preceding discussion, demonstrating the translation from abstract logic to tangible silicon.

The N-type devices are fabricated directly within the p-type substrate, as one might expect. Conversely, the P-type devices are constructed within a specially created n-type well (an “n-well”), which is essentially a localized region of n-type material embedded within the p-type substrate. To prevent a potentially destructive phenomenon known as latchup , a p-type substrate “tap” is diligently connected to V SS (ground), and an n-type n-well tap is connected to V DD (the positive voltage supply). These taps provide robust low-resistance paths to the power rails, shunting away parasitic currents that could otherwise trigger latchup and render the device inoperable. It’s an essential safeguard, preventing complex circuitry from self-destructing over something so trivial.

Cross section of two transistors in a CMOS gate, in an n-well CMOS process

Power: switching and leakage

One of the most compelling reasons for CMOS’s widespread adoption is its inherently superior power efficiency. Unlike older NMOS logic circuits, which dissipate power continuously whenever a transistor is in the ‘on’ state (due to a persistent current path from Vdd to Vss through the load resistor and the n-type network), CMOS logic primarily dissipates power only during the brief moments when it is actively switching its state. This is what we refer to as “dynamic power.” On a typical modern application-specific integrated circuit (ASIC) fabricated using a contemporary 90 nanometer process, for instance, the output transition might take a mere 120 picoseconds, occurring perhaps once every ten nanoseconds. This intermittent power draw is a game-changer.

Static CMOS gates are, frankly, remarkably power efficient, consuming virtually no power when they are idle and not actively switching. Historically, when designing chips, the total power consumption of CMOS devices was not the primary concern; factors like operating speed and chip area tended to dominate the design parameters. However, as CMOS technology relentlessly scaled down below sub-micron levels, the power consumption per unit area of the chip began to increase dramatically. This shift transformed power consumption from a secondary consideration into a critical design constraint, demanding constant innovation.

Broadly speaking, power dissipation in CMOS circuits can be categorized into two primary components: static dissipation and dynamic dissipation. Each presents its own set of challenges and requires specific mitigation strategies.

Static dissipation

Both NMOS and PMOS transistors are characterized by a gate–source threshold voltage (V th ). Below this threshold, the current flowing through the device—known as the subthreshold current—drops off exponentially, but it doesn’t disappear entirely. In earlier generations, CMOS circuits typically operated at supply voltages significantly higher than their threshold voltages (e.g., V dd might have been 5 V, while V th for both NMOS and PMOS was around 700 mV). This wide margin helped keep subthreshold leakage negligible. A specialized type of transistor, occasionally employed in some CMOS circuits, is the native transistor , which is characterized by a near-zero threshold voltage .

The silicon dioxide (SiO₂) layer, while an excellent insulator, is not perfect, especially at the incredibly small thicknesses found in modern processes. At these minute dimensions, electrons can, rather inconveniently, quantum tunnel across the extremely thin insulation. The probability of this tunneling current occurring decreases exponentially with increasing oxide thickness, making it a particularly significant concern for transistors fabricated below 130 nm technology nodes, where gate oxides are typically 20 Å (2 nm) or thinner. This quantum phenomenon is no longer a theoretical curiosity but a practical design challenge.

Furthermore, small reverse leakage currents are generated due to the formation of reverse bias junctions between various diffusion regions and wells (for example, between a p-type diffusion region and an n-well), as well as between wells and the substrate itself (e.g., an n-well and a p-substrate). In contemporary fabrication processes, these diode leakage currents are generally quite small when compared to the dominant subthreshold and tunneling currents, and thus, they can often be safely disregarded during detailed power calculations.

A critical, often overlooked, aspect is the precise matching of transistor ratios. If the current-driving capabilities of the PMOS and NMOS transistors within a complementary pair are not carefully balanced, it can lead to an imbalance. This imbalance can cause improper current flow, leading the CMOS device to unnecessarily heat up and dissipate power, even in a static state. Moreover, recent studies have indicated a rather ironic trade-off: leakage power can actually decrease due to the effects of aging, but this comes at the cost of the devices becoming progressively slower. [52] Time, it seems, takes its toll on everything.

To meet the ever-increasing demand for faster designs, manufacturers have transitioned to transistor constructions that feature lower voltage thresholds. However, this comes with a significant drawback: a modern NMOS transistor with a V th of, say, 200 mV, now exhibits a measurable and significant subthreshold leakage current. This means that even in designs like desktop processors, which contain a vast number of circuits that are not actively switching at any given moment, power is still consumed due to this persistent leakage current. Indeed, leakage power has become a substantial fraction of the total power consumed by such sophisticated designs.

One clever approach to managing this pervasive leakage power is Multi-threshold CMOS (MTCMOS), a technique now readily available from foundries. With MTCMOS, designers strategically employ high V th transistors in circuit paths where switching speed is not a critical constraint, while reserving low V th transistors for speed-sensitive paths where performance is paramount. Further technological advancements, particularly those utilizing even thinner gate dielectrics, introduce an additional leakage component due to current tunnelling through the extraordinarily thin gate dielectric. The adoption of high-κ dielectrics as a replacement for the conventional silicon dioxide gate dielectric offers a promising solution. These new materials allow for similar device performance while enabling a thicker gate insulator, thereby effectively mitigating this tunneling current. The relentless reduction of leakage power through both novel materials and innovative system designs is absolutely critical for the sustained scaling of CMOS technology into even smaller geometries. [53] The universe may be expanding, but our transistors are doing the opposite.

Dynamic dissipation

Charging and discharging of load capacitances

CMOS circuits, in their very nature, dissipate power primarily through the process of charging and discharging various load capacitances. These capacitances are predominantly composed of the gate and wire capacitances within the circuit, though drain and some source capacitances also contribute. This dynamic power dissipation occurs whenever the circuit is actively switched. Over one complete cycle of CMOS logic operation, current first flows from V DD to the load capacitance, charging it up. Subsequently, during the discharge phase, the accumulated charge flows from the now-charged load capacitance (C L ) to ground. Therefore, for a single, complete charge/discharge cycle, a total charge of Q=C L V DD is effectively transferred from V DD to ground. To calculate the current drawn, one simply multiplies this charge by the switching frequency on the load capacitances. Multiplying by the average voltage once more then yields the characteristic switching power dissipated by a CMOS device:

$$P = 0.5CV^2f$$

However, it’s a rare occurrence for most gates in a complex system to operate or switch during every single clock cycle . Consequently, this formula is often refined by the inclusion of a factor, $\alpha$, which is known as the activity factor. With this adjustment, the dynamic power dissipation can be more accurately expressed as:

$$P = \alpha CV^2f$$

A clock signal within a system, by its very definition, possesses an activity factor $\alpha=1$, as it reliably rises and falls in every single cycle. Most data signals, on the other hand, typically exhibit a more modest activity factor, often around 0.1. [54] By meticulously estimating the correct load capacitance at a given node and accurately determining its corresponding activity factor, the dynamic power dissipation at that specific node can be calculated with considerable precision. This granular understanding is essential for efficient power management in complex chip designs.

Short-circuit power

Given that both pMOS and nMOS transistors possess a finite rise/fall time during their transitions, there exists a brief, unavoidable period when both transistors are simultaneously ‘on.’ For example, during a transition from an ‘off’ to an ‘on’ state, there’s a small window where current can find a direct, low-resistance path from V DD straight to ground. This creates what is known as a short-circuit current , sometimes rather colloquially referred to as a “crowbar current.” The magnitude of this short-circuit power dissipation increases proportionally with the rise and fall times of the transistors.

This particular form of power consumption became increasingly significant throughout the 1990s, as interconnecting wires on chips became progressively narrower and, consequently, more resistive. CMOS gates situated at the end of these increasingly resistive wires experience slower input transitions, exacerbating the crowbar current effect. While careful design practices, specifically those that meticulously avoid weakly driven, long, skinny wires, can certainly mitigate this effect, crowbar power can nonetheless account for a substantial portion of the total dynamic power consumed by a CMOS circuit. It’s a testament to the fact that even in highly optimized systems, perfection remains an elusive ideal.

Input protection

Parasitic transistors, those unwelcome but inherent byproducts of the CMOS structure, can be inadvertently activated by input signals that fall outside the normal operating range. Such aberrant signals might arise from transient events like electrostatic discharges (ESD) or unwanted line reflections . When these parasitic elements are triggered, they can initiate a destructive phenomenon known as latch-up , which has the potential to severely damage or even completely destroy the CMOS device. To combat this, robust clamp diodes are meticulously integrated into CMOS circuits. These diodes are designed to shunt away excessive current from such out-of-range signals, thereby protecting the delicate internal circuitry. Manufacturers’ data sheets, for the discerning engineer, will always specify the maximum permissible current that these protective diodes can safely handle. Ignoring such warnings is, predictably, ill-advised.

Analog CMOS

Further information: CMOS amplifier and Mixed-signal integrated circuit

While CMOS technology is undeniably the workhorse of the digital domain, its utility is by no means confined to it. It has found equally compelling applications in the realm of analog electronics . For instance, numerous high-performance CMOS operational amplifier ICs are readily available on the market, demonstrating its capability in continuous signal processing. Beyond amplifiers, transmission gates , which are essentially CMOS-based switches, can be ingeniously employed as analog multiplexers , offering a solid-state alternative to traditional signal relays . Furthermore, CMOS technology is extensively utilized for high-frequency RF circuits, operating all the way up to microwave frequencies, and is absolutely indispensable in mixed-signal (analog+digital) applications where the seamless integration of both domains is paramount. [citation needed] Its adaptability truly knows few bounds.

RF CMOS

Main article: RF CMOS

RF CMOS refers specifically to RF circuits (radio frequency circuits) that are fundamentally based on mixed-signal CMOS integrated circuit technology. These circuits are not merely common; they are ubiquitous in the landscape of modern wireless telecommunication technology. The development of RF CMOS is largely credited to Asad Abidi during his tenure at UCLA in the late 1980s. This innovation was nothing short of revolutionary, fundamentally altering the design paradigm for RF circuits and leading to the wholesale replacement of discrete bipolar transistors with integrated CMOS circuits in radio transceivers . [55]

This shift had profound implications, enabling the creation of sophisticated, remarkably low-cost, and truly portable end-user terminals. It ushered in an era of small, power-efficient, and easily portable units for an expansive array of wireless communication systems. This technological leap facilitated “anytime, anywhere” communication, directly contributing to, and indeed helping to bring about, the entire wireless revolution that has fueled the explosive growth of the wireless industry. [56]

Today, the baseband processors [57] [58] and radio transceivers found in every modern wireless networking device and mobile phone are mass-produced using RF CMOS devices. [55] These circuits are the silent workhorses, widely employed to transmit and receive wireless signals across an astonishing variety of applications. This includes critical infrastructure like satellite technology (such as GPS ), short-range personal area networks like Bluetooth , local area networks like Wi-Fi , vast mobile networks (including 3G and 4G ), terrestrial broadcast systems, and even advanced automotive radar applications, among countless other uses. [59]

Examples of commercially successful RF CMOS chips abound, including Intel ’s chips for DECT cordless phones and the ubiquitous 802.11 (Wi-Fi ) chips developed by companies such as Atheros . [60] Commercial RF CMOS products are also the foundational technology for Bluetooth and wireless LAN (WLAN) networks. [61] Further demonstrating its versatility, RF CMOS is also integral to the radio transceivers supporting crucial wireless standards like GSM , Wi-Fi, and Bluetooth, as well as the transceivers for modern mobile networks like 3G, and the remote units within sophisticated wireless sensor networks (WSN). [62]

The significance of RF CMOS technology to contemporary wireless communications, encompassing both wireless networks and mobile communication devices, cannot be overstated. Among the companies that have most effectively commercialized RF CMOS technology is Infineon . Its bulk CMOS RF switches now sell over 1 billion units annually, having reached a staggering cumulative total of 5 billion units as of 2018 [update]. [63] It’s a testament to the quiet power of efficiency.

Temperature range

Conventional CMOS devices are generally designed and rigorously tested to operate reliably across a broad temperature range, typically spanning from a chilly −55 °C to a scorching +125 °C. This wide operational window allows them to function in diverse environments, from automotive under-hood applications to industrial control systems.

However, theoretical predictions as early as August 2008 hinted at something far more extreme: that silicon CMOS could potentially function even at cryogenic temperatures, specifically down to −233 °C (a frigid 40 K ). [64] This theoretical possibility has since been empirically verified. Functioning temperatures remarkably close to 40 K have indeed been achieved in practice, notably with overclocked AMD Phenom II processors, albeit requiring an impressive combination of liquid nitrogen and liquid helium cooling. [65] It seems even silicon can endure the cold, given enough encouragement.

Pushing the boundaries in the opposite direction, Silicon carbide CMOS devices have demonstrated remarkable resilience, having been tested for an entire year at an astonishing 500 °C. [66] [67] This capability opens up entirely new frontiers for electronics in extremely high-temperature environments, such as deep-well drilling, aerospace, and even the interior of certain planetary probes.

Single-electron MOS transistors

Delving into the truly minuscule, ultra-small MOSFETs (with dimensions as tiny as L = 20 nm, W = 20 nm) are capable of achieving the single-electron limit when operated at cryogenic temperatures. This operational window typically spans from an extremely cold −269 °C (a mere 4 K ) up to approximately −258 °C (15 K ). Under these conditions, the transistor exhibits the fascinating phenomenon known as Coulomb blockade . This occurs due to the progressive charging of electrons, one by one, into the device’s channel. The number of electrons confined within this channel is precisely controlled by the gate voltage, allowing it to be set starting from an occupation of zero electrons, and then incrementally to one or many. [68] This level of control, at the very quantum limit, represents the ultimate frontier of miniaturization and precision in semiconductor technology. It’s a stark reminder that even the smallest things hold the most profound secrets.

See also

• Beyond CMOS – Possible future digital logic technologies
• Gate equivalent – Measure of circuit complexity
• HCMOS – Specifications for the 74HC00 IC family
• LVCMOS – Class of digital integrated circuits
• sCMOS – Camera technology

Notes

• ^ a b Transistors symbols show here are simplified logic symbols and not electrical schematic symbols.